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CSEM, MIFS Demonstrate World-Record Lows in Energy Consumption for a Microcontroller

A 32-bit RISC microcontroller designed in C55DDC was presented at IEEE CICC in Austin, TX, demonstrating only 2.5uW/MHz.

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By: Anthony Locicero

Copy editor, New York Post

The growth of the Internet of Things and wearable technologies, combined with edge processing, is placing ever-greater demands on low-power electronics. Smart dust and unobtrusive wearables require tiny batteries or even self-powering, harvesting energy from their surroundings.

CSEM and Mie Fujitsu Semiconductor have joined forces to develop a near-threshold 0.5V ecosystem. Since energy scales with the square of the supply voltage, huge reductions in energy consumption can be achieved for similar performance. MIFS’ Deeply Depleted Channel (DDC) technology is perfectly adapted to low-power applications, while its immunity to random dopant fluctuations makes it suitable for low-voltage operation. Low-voltage operation, however, is still subject to process and temperature and other variations. To overcome the impact from these variations CSEM and MIFS applied a variety of design techniques and implemented Body-bias-based Adaptive Dynamic Frequency Scaling (ADVbbFS) as one of the key IPs.

A 32-bit RISC microcontroller designed in C55DDC was presented recently at IEEE CICC in Austin, TX, demonstrating only 2.5uW/MHz – a new world record in a 55nm CMOS process.

“Combining CSEM’s ULP design experience with MIFS’ DDC process technology helps realize IOT chip designs that are unbeatable in energy efficiency,” said Keizaburo Yoshie, Senior VP, MIFS,

“Low-voltage design is essential for the next generation of IOT devices,” added Alain-Serge Porret, CSEM’s VP, Integrated & Wireless Systems”We were delighted to team up with MIFS to make this dream a reality.”

A complete design ecosystem is now available, including a process design kit with all libraries and key analogue IP blocks.

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